Conventionally, a computer system is known in which a plurality of system boards (SBs) constituted by a Central Processing Unit (CPU), an Input Output (IO) mechanism, a memory, and a system controller (SC) are connected by a cross bar system constituted by a plurality of cross bar boards (XBBs).
Here, to efficiently perform data transfer through a bus between the cross bar boards, for example, as a conventional technique, a transaction issuance control method of a parallel computer system in which a broadcast packet of broadcast (BC) transferred from a CPU of a system board to all the CPUs of all the system boards and a unicast packet of unicast (UC) transferred from a CPU of a system board to another CPU of another system board are input into a selector, and the unicast packet is preferentially-transferred to the bus between the cross bar boards is proposed.
Furthermore, for example, as a conventional technique, a disk array control device including two types of buses which are a broadcast bus for transferring broadcast packets and a unicast bus for transferring unicast packets as transfer paths between the cross bar boards is proposed.    [Patent Document 1] Japanese Laid-open Patent Publication No. 2002-169786    [Patent Document 2] Japanese Laid-open Patent Publication No. 2000-267816
However, in the above conventional technique, transfer/reception delay of the broadcast packet may be caused because the unicast packet is preferentially-transferred to the bus between the cross bar boards.
Also, in the above conventional technique, the broadcast bus and the unicast bus are not used efficiently as a whole because the number of the unicast packets is overwhelmingly greater than the number of the broadcast packets and packet congestion occurs in the unicast bus while the broadcast packet is not transferred at all in the broadcast bus.